PDP-1 FPGA Implementation in Verilog, with CRT, Teletype and Console

To simulate phosphor decay, a classic straightforward approach would require at least 1024 x 1024 (DEC Type 30 CRT resolution) pixels x 8 bit per pixel = 8 Mbits of memory. It buffers the next 8 rows and fills them with pixels seen at the shift register taps whose Y coordinate matches one of the buffer rows. It was then converted to a 1-bit black and white image and written to a console background ROM as a memory image file.

Source: github.com