Fairylog: A Racket language aiming to be like Verilog

This post will provide a short introduction to Fairylog by way of building some custom hardware to read a pair of Nintendo pads. Fairylog is a Racket language (of course) which aims to be quite like Verilog, with less redundant syntax, Racket macros, and several additional compile-time features that Verilog seems to be lacking. note: because Verilog and Racket share some forms with the same name, if you explicitly need a Racket one in some ad-hoc code, they have been renamed to have a r: prefix, eg (r:begin …) (r:case …)

This code is so common in Verilog that it quickly becomes tiring to write it all the time.

Source: pinksquirrellabs.com