Sidestepping Moore’s Law

ASE’s FoCoS packaging technology has demonstrated that wafer-level fan-out supports heterogenous integration for multi-die, ASIC and memory integration, with the potential of reduced package costs. SE: Chiplets, fan-out and other packaging technologies enable so-called heterogeneous integration. SE: If the industry continues to use today’s interconnect technologies, like copper pillars and microbumps, what does that mean for IC packaging in advanced chip designs?

Source: semiengineering.com