Performance Speed Limits

You can do that by:

Intel, AMD: One operation per port, per cycle

Let us use our newfound knowledge of the pipeline width limitation, and tackle another example loop:

The loop compiles to the following assembly. You can get this information from Agner’s instruction tables:

On modern Intel some simple integer arithmetic ( , , , ), bitwise ( , , ) and test ( , ) run on four ports, so you aren’t very likely to see a port bottleneck for these operations (since the pipeline width bottleneck is more general and is also four), but many operations complete for only a few ports. Modern Intel and AMD chips (and many others) have a limit of two loads per cycle, which you can achieve if both loads hit in L1.

Source: travisdowns.github.io