Ethernet MDIO / MMD Design for FPGA Open Source Network Processor

A review of Ethernet Management Bus basics, architecture, and design with the aid of oscilloscope screen shots for FPGA-based open source networking project

The Private Island open source FPGA networking project integrates an MDIO controller to offload the exteral micro controller (µC) and enable real-time, parallel communication with Ethernet PHYs. Per IEEE 802.3-2018, clause 22, the FPGA performs Station Management (STA) via the two wire management bus, which consists of a clock (MDC) and a data signal (MDIO) (see 22.2.2.13 – 22.2.2.14). Figure 3 shows a scope trace of an MDIO read cycle performed by the FPGA at register address 0x3 of the DP83867.

Source: mindchasers.com