Making Chip Packaging Simpler

Even within the same type of packaging approach, such as fan-out, there are chip first and chip last approaches. “We are seeing the introduction of more advanced system in package (SiP), fan-out on substrate, and 2.5D chip on wafer packages,” said Warren Flack, vice president of worldwide lithography applications at Veeco. “The major lithography challenges going forward for these advanced fan-out packages are imaging submicron RDL with high aspect ratios, minimizing overlay errors that occur from die shifting, extremely warped substrate handling, and support for very large 2.5D chip on wafer package sizes.

Source: semiengineering.com