SMoTherSpectre: Transient execution attacks through port contention

The former is used to denote the capability to execute a thread, while the latter is the physical implementation of a unit (execution pipeline, registers, caches) called a core. Suppose threads A (Attacker) and V (Victim) run on the same physical Skylake core, where is scheduled by port 1 and is scheduled by port 5. For SMoTher-gadgets, conditional branches where the two subsequent paths are SMoTher-differentiable, the attacker can figure out if the branch was taken or not taken by introducing contention on one or more ports which the target and fallthrough use for different number of cycles.

Source: nebelwelt.net