SweRV – An Annotated Deep Dive of the SweRV RISC-V Core

Keeping their promise of a year earlier, Western Digital also announced that the core would be available as open source under a liberal Apache 2.0 open source license, with instruction set simulator (ISS) and testbenches included as well! If the pipeline diagram correctly reflects that architecture of the SweRV core, there’s a forwarding path from to , which allows to use the result of the instruction. We can see in the diagram that no bubbles were inserted between and , something that would have been impossible without the retry stage: a hypothethical SweRV core without retry ALU units would have required a bubble of 1 clock cycle: sufficient to line up at the stage on cycle 5, when the result of is first available.

Source: tomverbeure.github.io