TSMC and OIP Deliver Industry’s First Complete Design Infrastructure 5nm Process

TSMC’s comprehensive 5nm design infrastructure includes the full versions of the 5nm Design Rule Manual (DRM), SPICE model, process design kits (PDKs) and silicon-validated foundation and interface IP, and also supports a full range of certified EDA tools and design flows. Through the certification program, TSMC and EDA partners enabled design tools to support TSMC 5nm design rules, ensured required accuracy, and improved routability for optimized power, performance and area (PPA) for our customers to take full advantage of TSMC’s 5nm process technology. To further support the production delivery of TSMC’s 5nm design infrastructure, Cadence has undergone TSMC’s latest 5nm v1.0 certification process and delivered IP and integrated tools, flows and methodologies that support both traditional and cloud-based environments, including TSMC’s OIP Virtual Design Environment, to ensure that customers have a seamless user experience.

Source: www.tsmc.com